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This paper reports on the transient photocurrent measurements made with test structures fabricated on sapphire substrates, and the computer simulation model which was developed to use the test results. Predictions of logic upset for a 4 K RAM CMOS/SOS compared with measured upset rates showed agreement within a factor of 2. The test structure results indicate that the sapphire photoconductance is 6.3 x 10 to the -19th mhos/(rads/s)-micron. The use of this value in the present simulation model will increase the predicted u ...
Published by: IEEE Transactions on Nuclear Science Published on: 12/1986
YEAR: 1986   DOI: 10.1109/TNS.1986.4334608
CMOS; Electric Current; Electronics and Electrical Engineering; Logic Circuits; parker solar probe; Photoconductivity; Radiation Damage; Random Access Memory; Sapphire; Solar Probe Plus; Sos (Semiconductors)