TitleA 40 ns CMOS E/SUP 2/PROM
Publication TypeJournal Article
Year of Publication1982
AuthorsStewart, RG, Plus, D
JournalIEEE Journal of Solid-State Circuits
Volume17
Issue5
Pagination841 - 846
Date Published10/1982
ISSN0018-9200
Keywordsparker solar probe; PROM, Delay, Decoding, Power dissipation, Logic circuits, Detectors, Trigger circuits, Power generation, Signal generators, Logic functions; Solar Probe Plus
Abstract

New high-performance CMOS circuit techniques have been developed and used to build an 8K E/SUP 2/PROM with an access time of 38 ns at 5 V. Using standard CMOS/SOS technology, the device dissipates only 0.8 mW quiescent power at 5 V and 60 mW at 1 MHz. A midpoint precharge and sense technique permits operation form a supply voltage of 4-12 V.

URLhttp://ieeexplore.ieee.org/document/1051828/http://xplorestaging.ieee.org/ielx5/4/22585/01051828.pdf?arnumber=1051828
DOI10.1109/JSSC.1982.1051828
Short TitleIEEE J. Solid-State Circuits


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